Technological Field
The present disclosure relates to a technique for controlling timing to output a stop signal indicating stop of voltage supply.
Description of the Related Art
Power supply devices which output a stop signal indicating stop of a power supply before stopping voltage supply have been widely used. The stop signal is output before the power supply device stops completely. Accordingly, an external apparatus which receives the stop signal can perform stop preparation processing (such as backup processing, for example) in preparation for the stop of the power supply, before the power supply device stops completely.
Regarding techniques for performing backup processing based on a stop signal, Japanese Laid-Open Patent Publication No. 08-149686 discloses a power supply device “which detects a power failure of a direct current (DC) power supply for an apparatus, and allows processing of saving data stored in a memory within the apparatus”. Japanese Laid-Open Patent Publication No. 2002-236528 discloses a power supply device “capable of saving unprocessed data in a memory when an alternating current (AC) input voltage decreases”.
It takes time from when an instruction to stop voltage supply is received to when voltage supply to an external apparatus stops completely. If a stop signal is output frequently during this period, the external apparatus repeatedly performs stop preparation processing such as backup processing and system reset. Further, when a stop signal is output too early, the stop preparation processing is started although there is enough time to perform the stop preparation processing. Therefore, in order to make time given for the stop preparation processing constant, it is desired to appropriately control timing to output a stop signal.
The power supply devices disclosed in Japanese Laid-Open Patent Publication No. 08-149686 and Japanese Laid-Open Patent Publication No. 2002-236528 each output a stop signal when an input voltage is less than a predetermined value. Accordingly, the power supply devices can each delay output of the stop signal, and suppress the number of times the stop signal is output. However, the time taken from when an instruction to stop voltage supply is received to when voltage supply to an external apparatus stops completely varies according to a magnitude of a load connected to the power supply device. Accordingly, in the power supply devices disclosed in Japanese Laid-Open Patent Publication No. 08-149686 and Japanese Laid-Open Patent Publication No. 2002-236528, time taken from when the stop signal is output to when voltage supply stops completely varies according to the magnitude of a load connected to each power supply device. Therefore, the stop signal may be output frequently, and backup processing and system reset processing may be performed repeatedly.
The present disclosure has been made to solve the aforementioned problem, and an object of the present disclosure in an aspect is to provide a power supply device capable of making time taken from when a stop signal is output to when voltage supply stops constant. An object of the present disclosure in another aspect is to provide a control method capable of making time taken from when a stop signal is output to when voltage supply stops constant.